As integrated circuits on semiconductor chips became denser, faster and more complex, their electrical performance requirements became higher and the need for greater heat sink capacity became greater. Consequently these integrated circuits required both greater and more effective capacitive decoupling and improved heat sink capacity.
Effective capacitive decoupling in integrated circuits has, in the past, been provided by several different methods. One approach added discrete decoupling capacitors onto the package containing the integrated semiconductor chip. Another approach added the capacitor in available regions in the circuitry itself. The latest approach utilizes the substrate of the chip itself as a capacitive plate with the other plate being comprised of an insulatively coated metallic deposit formed on the back or inactive major surface of the chip.
Each of these approaches have drawbacks. In the first, because the decoupling capacitor is quite remote from the active circuitry on the chip, they provide, at best, only marginal decoupling and no known heat sink capability.
In the second, as the circuitry, on the chip, became denser, the need of larger and better decoupling capacitors that could handle larger on chip voltages or voltage spikes became greater just as the free area into which such capacitors could be placed became reduced. Thus the capacitors became smaller and any heat sinking capacity that they might have provided became similarly reduced.
The latest approach which utilizes the chip substrate as the first plate of the coupling capacitor with the other plate being comprised of an insulatively coated metallic deposit formed on the back or inactive major surface of the chip not only reduced the ability to affix heat sinks onto the chip but the insulation on the surface of the second plate increased the thermal heating effects in the devices on the chip leading to the possibility of reduced electrical performance in the circuitry.
Silicon on insulator (SOI) technology provides enhanced performance by reduction of MOSFET junction capacitance. The power (P) of a semiconductor chip is a function of chip capacitance (C), power supply voltage (V), and the transition frequency (f), i.e., P=CV.sup.2 f. While the decrease in chip capacitance is an advantage for power reduction and enhanced chip performance, the decrease in chip capacitance is a concern for noise, electrostatic discharge, (ESD) and stability. Therefore in silicon on insulator (SOI) devices there is a need for extra capacitance to improve total chip capacitance. This is achieved with decoupling capacitors.